OSPEN: an open source platform for emulating neuromorphic hardware

This paper demonstrates a framework that entails a bottom-up approach to accelerate research, development, and verification of neuro-inspired sensing devices for real-life applications. Previous work in neuromorphic engineering mostly considered application-specific designs which is a strong limitation for researchers to develop novel applications and emulate the true behaviour of neuro-inspired systems. Hence to enable the fully parallel brain-like computations, this paper proposes a methodology where a spiking neuron model was emulated in software and electronic circuits were then implemented and characterized. The proposed approach offers a unique perspective whereby experimental measurements taken from a fabricated device allowing empirical models to be developed. This technique acts as a bridge between the theoretical and practical aspects of neuro-inspired devices. It is shown through software simulations and empirical modelling that the proposed technique is capable of replicating neural dynamics and post-synaptic potentials. Retrospectively, the proposed framework offers a first step towards open-source neuro-inspired hardware for a range of applications such as healthcare, applied machine learning and the internet of things (IoT)

Characterising lateral capacitance of MNOSFET with localised trapped charge in nitride layer

This paper discusses the limitations of scanning microscope to read localised charge and proposes a viable solution. A 2D simulation and characterisation of the capacitance-voltage (C-V) characteristics of the lateral source-base transition of metal-nitride-oxide-semiconductor field effect transistor (MNOSFET) with charge trapped in nitride layer is presented. It is shown that C-V dependence is changed after trapping the localised charge in nitride layer. The change depends on position of the localised trapped charge. An n-channel transistor is considered with acceptor concentration in base of 1016 cm−3. By localising a charge bit with linear size of 80 nm in nitride layer, it is observed that capacitance jump in C-V dependence starts at some bias voltage applied to the source-base transition. This voltage depends on the position of charge bit. This dependence can be used in determining the charge bit position in the nitride layer along channel. To the best of the author’s knowledge, it is one of the most efficient methods in scanning localised charge

A Tract Reflection on Challenges in Research & Development for New Product Development in the Industrial Sector of Pakistan

New Product Development (NPD) is a strategic issue of successful business in the competitive era of the new global economy. Pakistan is rel atively small, in the Asian region, yet a promising nation in the South East Asian region. Unfortunately, over the past few decades,the country’s export performance has remained sluggish due to slower growth of NPD in her industrial sector.The present st udy conceptually examines the issue of challenges and remedial strategies involved in the context of R&D in the process of NPD in Pakistani industries at-large.Indeed, textile industry is currently a major segment (46%) of the Pakistani industrial sector.In general,the focus of the study is on NPD strategic criteria of the nation.The study discusses global and inward challenges and spells out the steps in formulating a new strategy towards NPD.Pakistan policy makers need to identify and focus on policies towards improvement of FDI inflows, industrial education, technology advancement, R &D budget, and establishing the industrial cluster among several other factors as building blocks of the NDP

Step forward to map fully parallel energy efficient cortical columns on field programmable gate arrays

This study presents energy and area-efficient hardware architectures to map fully parallel cortical columns on reconfigurable platform - field programmable gate arrays (FPGAs). An area-efficient architecture is proposed at the system level and benchmarked with a speech recognition application. Owing to the spatio-temporal nature of spiking neurons it is more suitable to map such architectures on FPGAs where signals can be represented in binary form and communication can be performed through the use of spikes. The viability of implementing multiple recurrent neural reservoirs is demonstrated with a novel multiplier-less reconfigurable architectures and a design strategy is devised for its implementation

Accelerated Diagnosis of Novel Coronavirus (COVID-19)—Computer Vision with Convolutional Neural Networks (CNNs)

Early detection and diagnosis of COVID-19, as well as exact separation of non-COVID-19 cases in a non-invasive manner in the earliest stages of the disease, are critical concerns in the current COVID-19 pandemic. Convolutional Neural Network (CNN) based models offer a remarkable capacity for providing an accurate and efficient system for detection and diagnosis of COVID-19. Due to the limited availability of RT-PCR (Reverse transcription-polymerase Chain Reaction) test in developing countries, imaging-based techniques could offer an alternative and affordable solution to detect COVID-19 symptoms. This case study reviewed the current CNN based approaches and investigated a custom-designed CNN method to detect COVID-19 symptoms from CT (Computed Tomography) chest scan images. This study demonstrated an integrated method to accelerate the process of classifying CT scan images. In order to improve the computational time, a hardware-based acceleration method was investigated and implemented on a reconfigurable platform (FPGA). Experimental results highlight the difference between various approximations of the design, providing a range of design options corresponding to both software and hardware. The FPGA based implementation involved a reduced pre-processed feature vector for the classification task which is a unique advantage for this particular application. To demonstrate the applicability of the proposed method, results from the CPU based classification and the FPGA were measured separately and compared retrospectively

Using Deep Neural Networks to Classify Symbolic Road Markings for Autonomous Vehicles

To make autonomous cars as safe as feasible for all road users, it is essential to interpret as many sources of trustworthy information as possible. There has been substantial research into interpreting objects such as traffic lights and pedestrian information, however, less attention has been paid to the Symbolic Road Markings (SRMs). SRMs are essential information that needs to be interpreted by autonomous vehicles, hence, this case study presents a comprehensive model primarily focused on classifying painted symbolic road markings by using a region of interest (ROI) detector and a deep convolutional neural network (DCNN). This two-stage model has been trained and tested using an extensive public dataset. The two-stage model investigated in this research includes SRM classification by using Hough lines where features were extracted and the CNN model was trained and tested. An ROI detector is presented that crops and segments the road lane to eliminate non-essential features of the image. The investigated model is robust, achieving up to 92.96 percent accuracy with 26.07 and 40.1 frames per second (FPS) using ROI scaled and raw images, respectively